Publication List

2024

Conference Papers (Refereed)

• T. Tanigawa, M. Noda, and N. Ishiura: "Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2024), pp. 32-37 (Mar. 2024). [pdf]
• N. Yoshida, T. Hamada, and N. Ishiura: "Native Code Level Test of Optimizing Performance of Android Compilers," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2024), pp. 181-186 (Mar. 2024). [pdf]
• M. Noda and N. Ishiura: "Enumeration of Genaralized Parallel Counters for Multi-Input Adder Synthesis for FPGAs," in Proc. Asia and Pacific Conference on Circuits and Systems (APCCAS 2024), pp. 64-68 (Nov. 2024). [pdf]

Technical Reports

• (in Japanese) K. Mikami, N. Ishiura, H. Tomiyama, and H. Kanbara: "Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems," Technical Report of IEICE, VLD2023-94, (Jan. 2024). [pdf]
• (in Japanese) S. Kishimoto and N. Ishiura: "Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer," Technical Report of IEICE, VLD2023-95, (Jan. 2024). [pdf]
• (in Japanese) M. Noda and N. Ishiura: "Enumeration of Generalized Parallel Counters for Compressor Tree Synthesis," IPSJ Design Automation Symposium 2022, pp. 106-112 (Aug. 2024). [pdf]

2023

Conference Papers (Refereed)

• M. Nakahara and N. Ishiura: "Arrival Order Processing of Service Requests in Full Hardware Implementation of RTOS-Based Systems," in Proc. International Technical Conference on Circuit/Systems, Computers and Communications (ITC-CSCC 2023), pp. 467-472 (June 2023). [pdf]
• H. Minamiguchi, N. Ishiura, H. Tomiyama, and H. Kanbara: "Automatic Generation of Management Module for Full Hardware Implementation of RTOS-Based Systems," in Proc. International Technical Conference on Circuit/Systems, Computers and Communications (ITC-CSCC 2023), pp. 473-478 (June 2023). [pdf]

Technical Reports

• (in Japanese) T. Tanigawa, M. Noda, and N. Ishiura: "Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree," Technical Report of IEICE, VLD2022-68, (Jan. 2023). [pdf]

2022

Conference Papers (Refereed)

• T. Ando, I. Muguruma, Y. Ishii, N. Ishiura, H. Tomiyama, and H. Kambara: "Full Hardware Implementation of RTOS-Based Systems Using General High-Level Synthesizer," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2022), pp. 2-7 (Oct. 2022). [pdf] Outstanding Paper Award
• H. Minamiguchi, M. Nakahara, Y. Ishii, Y. Shinohara, I. Muguruma, and N. Ishiura: "Hardware RTOS Services for Full Hardware Implementation of RTOS-Based Systems," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2022), pp. 14-19 (Oct. 2022). [pdf]
• R. Nakamichi, S. Kishimoto, N. Ishiura, and T. Kondo: "Binary Synthesis Using High-Level Synthesizer as its Back-End," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2022), pp. 121-126 (Oct. 2022). [pdf]

Technical Reports

• (in Japanese) T. Ando, Y. Ishii, N. Ishiura, H. Tomiyama, and H. Kanbara: "Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer," Technical Report of IEICE, VLD2021-51, (Jan. 2022). [pdf]
• (in Japanese) Y. Shinohara and N. Ishiura: "Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems," Technical Report of IEICE, VLD2021-52, (Jan. 2022). [pdf]
• (in Japanese) N. Yoshida and N. Ishiura: "Testing of Optimization Performance of Android DEX Compilers Based on Native Code Comparison," Technical Report of IEICE, VLD2021-74, (Jan. 2022). [pdf]
• (in Japanese) H. Minamiguchi, N. Ishiura, H. Tomiyama, and H. Kanbara: "Automatic Generation of Management Hardware for Full Hardware Implementation of RTOS-Based Systems," IPSJ Design Automation Symposium 2022, pp. 83-88 (Aug. 2022). [pdf]
• (in Japanese) M. Nakahara and N. Ishiura: "Arrival Order Release of Wait of Service Requests in Full Hardware Implementation of RTOS-Based Systems," IPSJ Design Automation Symposium 2022, pp. 89-95 (Aug. 2022). [pdf]

2021

Conference Papers (Refereed)

• N. Ishiura and R. Saimyoji: "Compact FPGA Implementation of Popcounter for BNN Using Linear Feedback Shift Register," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2021), R3-11, pp. 179-180 (Mar. 2021). [pdf]
• W. Nakano, Y. Shinohara, and N. Ishiura: "Full Hardware Implementation of FreeRTOS-Based Real-Time Systems," in Proc. IEEE Region 10 Conference (TENCON 2021), pp. 435-440 (Dec. 2021). [pdf]

Technical Reports

• (in Japanese) N. Namba and N. Ishiura: "Mutation-Based Fuzzing Using Data Structure Captured via Data Generator," Technical Report of IEICE, VLD2020-64, (Jan. 2021). [pdf]
• (in Japanese) Y. Azuma and N. Ishiura: "Detection of Vulnerability Inducing Code Elimination by Compiler Optimization Based on Binary Code Comparison," Technical Report of IEICE, VLD2020-65, (Jan. 2021). [pdf]
• (in Japanese) D. Murakami and N. Ishiura: "Performance Testing of VRP Optimization of C Compilers by Random Program Generation," Technical Report of IEICE, VLD2020-66, (Jan. 2021). [pdf]
• (in Japanese) I. Muguruma, N. Ishiura, T. Ando, H. Tomiyama, and H. Kanbara: "Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems," Technical Report of IEICE, VLD2020-75, (Mar. 2021). [pdf]
• (in Japanese) R. Nakamichi, N. Ishiura, and T. Kondo: "Binary Synthesis from RISC-V Executable Code Using General-Purpose High-Level Synthesizer," IPSJ Design Automation Symposium 2021, pp. 39-45 (Sept. 2021). [pdf]

2020

Technical Reports

• (in Japanese) H. Maeda and N. Ishiura: "Increasing Test Variation for C Compilers by Equivalent Mutant Generation," Technical Report of IEICE, VLD2019-61, (Jan. 2020). [pdf]
• (in Japanese) Y. Higuchi, N. Ishiura, and N. Namba: "Mutation Fuzzing Based on Type Estimation of Data Items Utilizing Data Writer," Technical Report of IEICE, VLD2019-62, (Jan. 2020). [pdf]
• (in Japanese) W. Nakano, N. Ishiura, H. Tomiyama, and H. Kambara: "Full Hardware Synthesis of FreeRTOS-Based Systems," Technical Report of IEICE, VLD2019-70, (Jan. 2020). [pdf]
• (in Japanese) S. Hamana and N. Ishiura: "Binary Synthesis from RISC-V Executables," Technical Report of IEICE, VLD2019-71, (Jan. 2020). [pdf]
• (in Japanese) N. Osako, H. Kanbara, and N. Ishiura: "Motor Current Signature Analysis Based On-Line Fault Detection of DC Motor," Technical Report of IEICE, VLD2019-, (Mar. 2020). [pdf]
• (in Japanese) H. Wakabayashi and N. Ishiura: "Hardware Control from Erlang Programs on Programmable SoC," Technical Report of IEICE, VLD2019-114, (Mar. 2020). [pdf]

2019

Conference Papers (Refereed)

• S. Ota and N. Ishiura: "Synthesis of Distributed Control Circuits for Dynamic Scheduling across Multiple Dataflow Graphs," in Proc. International Technical Conference on Circuit/Systems, Computers and Communications (ITC-CSCC 2019), pp. 639-642 (June 2019). [pdf]
• R. Sugimoto and N. Ishiura: "Parameter Embedding for Efficient FPGA Implementation of Binarized Neural Networks," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), R1-9, pp. 41-45 (Oct. 2019). [pdf]
• S. Hamana and N. Ishiura: "Binary Synthesis from RISC-V Executables (short paper)", in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), R3-12, pp. 227-228 (Oct. 2019). [pdf]
• Y. Azuma and N. Ishiura: "Detection of Vulnerability Guard Elimination by Compiler Optimization Based on Binary Code Comparison (short paper)", in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), R3-13, pp. 229-230 (Oct. 2019). [pdf]

Technical Reports

• (in Japanese) Y. Oosako, N. Ishiura, H. Tomiyama, and H. Kanbara: "Synthesis of Full Hardware Implementation of RTOS-Based Systems," Technical Report of IEICE, VLD2018-122, (Mar. 2019). [pdf]
• (in Japanese) R. Shimizu and N. Ishiura: "Reinforcing Generation of Instruction Sequences in Random Testing of Android Virtual Machine," Technical Report of IEICE, VLD2018-124, (Mar. 2019). [pdf]

2018

Conference Papers (Refereed)

• W. Nakano and N. Ishiura: "Extended Distributed Control for Dynamic Scheduling across Dataflow Graphs (short paper)", in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2018), R1-7, pp. 35-36 (Mar. 2018). [pdf]
• N. Osako, S. Ota, S. Yura, and N. Ishiura: "High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit (short paper)", in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2018), R2-13, pp. 159-160 (Mar. 2018). [pdf]
• Y. Oosako, N. Ishiura, H. Tomiyama, and H. Kanbara: "Synthesis of Full Hardware Implementation of RTOS-Based Systems," in Proc. International Symposium on Rapid System Prototyping (RSP 2018), pp. 1-7 (Oct. 2018). [pdf]
• S. Takakura, M. Iwatsuji, and N. Ishiura: "Extending Equivalence Transformation Based Program Generator for Random Testing of C Compilers," in Proc. ACM SIGSOFT International Workshop on Automating TEST Case Design, Selection, and Evaluation (A-TEST 2018), pp. 9-15 (Nov. 2018). [pdf]
• K. Kitaura and N. Ishiura: "Random Testing of Compilers' Performance Based on Mixed Static and Dynamic Code Comparison," in Proc. ACM SIGSOFT International Workshop on Automating TEST Case Design, Selection, and Evaluation (A-TEST 2018), pp. 38-44 (Nov. 2018). [pdf]

Technical Reports

• (in Japanese) K. Azuma, S. Hamana, H. Wakabayashi, N. Ishiura, N. Yoshida, and H. Kanbara: "Distributed Memory Architecture for High-Level Synthesis from Erlang," Technical Report of IEICE, VLD2017-75, (Jan. 2018). [pdf]
• (in Japanese) M. Iwatsuji and N. Ishiura: "Reinforcing Generation of Control Flow Statements in Random Test System of C Compilers Based on Equivalence Transformation," Technical Report of IEICE, VLD2017-87, (Jan. 2018). [pdf]
• (in Japanese) K. Tanaka, N. Ishiura, M. Nishimura, and A. Fukui: "Mutant Generation of Performance Tests for LLVM Back-Ends," Technical Report of IEICE, VLD2017-88, (Jan. 2018). [pdf]
• (in Japanese) H. Ikeo, R. Shimizu, and N. Ishiura: "Random Testing of Android Virtual Machine by Valid DEX File Generation," Technical Report of IEICE, VLD2017-88, (Feb. 2018). [pdf]
• (in Japanese) S. Takakura, M. Iwatsuji, and N. Ishiura: "Enriching Generation of Control Statements and Data Structures for Random Test System of C Compilers Based on Equivalence Transformation," IPSJ Design Automation Symposium 2018, pp. 9-14 (Aug. 2018). [pdf]

Convention Articles

• R. Sugimoto and N. Ishiura: "Parameter Embedding for FPGA Implementation of Binarized Neural Networks," Proc. IEICE Society Confenrece 2018, A-6-1, (Sept. 2018). [pdf]

2017

Journal Papers

• Y. Hibino, H. Ikeo, and N. Ishiura: "CF3: Test Suite for Arithmetic Optimization of C Compilers (letter)", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E100-A, no. 7, pp. 1511-1512 (July 2017). [link]

Conference Papers (Refereed)

• K. Hayashi and N. Ishiura: "Randomizing Cache Index Generation for FPGA Implementation," in Proc. International Technical Conference on Circuit/Systems, Computers and Communications (ITC-CSCC 2017), pp. 330-332 (July 2017). [pdf]
• K. Azuma, N. Ishiura, N. Yoshida, and H. Kanbara: "Distributed Memory Architecture for High-Level Synthesis of Embedded Controllers from Erlang," in Proc. ACM SIGPLAN International Workshop on Erlang 2017, pp. 13-19 (Sept. 2017). [pdf]
• N. Ito, Y. Oosako, N. Ishiura, H. Tomiyama, and H. Kanbara: "Binary Synthesis Implementing External Interrupt Handler as Independent Module," in Proc. International Symposium on Rapid System Prototyping (RSP 2017), pp. 92-98 (Oct. 2017). [pdf]
• M. Shimizu, N. Ishiura, S. Ota, and W. Nakano: "Speculative Execution in Distributed Controllers for High-Level Synthesis," in Proc. International Symposium on Rapid System Prototyping (RSP 2017), pp. 99-105 (Oct. 2017). [pdf]

Technical Reports

• (in Japanese) K. Kitaura and N. Ishiura: "Random Testing of C Compiler Optimization Performance Based on Comparison of Assembly Codes and Execution Time," IPSJ Design Automation Symposium 2017, pp. 39-44 (Aug. 2017). [pdf]

2016

Journal Papers

• A. Hashimoto and N. Ishiura: "Detecting Arithmetic Optimization Opportunities for C Compilers by Randomly Generated Equivalent Programs," IPSJ Transactions on System LSI Design Methodology, vol. 9, pp. 21-29 (Feb. 2016). [link] TSLDM Best Paper Award

Tutorials

• (in Japanese) N. Ishiura: "Compiler Fuzzing," IEICE Fundamentals Review, vol. 9, no. 3, pp. 188-196 (Jan. 2016). [link]

Conference Papers (Refereed)

• D. Fujiwara, N. Ishiura, R. Sakai, R. Aoki, and T. Ogawara: "Reverse Engineering from Mainframe Assembly to C Codes in Legacy Migration," in Proc. International Conference on Enterprise Architecture and Information Systems (EAIS 2016), pp. 1058-1063 (July 2016). [pdf]
• M. Iwatsuji, A. Hashimoto, and N. Ishiura: "Detecting Missed Arithmetic Optimization in C Compilers by Differential Random Testing (short paper)", in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016), R1-1, pp. 2-3 (Oct. 2016). [pdf]
• K. Tanaka, N. Ishiura, M. Nishimura, and A. Fukui: "Random Testing Back-end of Compiler Infrastructure LLVM (short paper)", in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016), R2-1, pp. 88-89 (Oct. 2016). [pdf]
• M. Shimizu and N. Ishiura: "Extending Distributed Control for High-Level Synthesis beyond Borders of Basic Blocks," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016), R3-1, pp. 172-177 (Oct. 2016). [pdf]
• H. Takebayashi, N. Ishiura, K. Azuma, N. Yoshida, and H. Kanbara: "High-Level Synthesis of Embedded Systems Controller from Erlang," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016), R4-2, pp. 285-290 (Oct. 2016). [pdf]
• N. Ishiura and Y. Oosako: "Introducing Real Constraints in Partitioned ILP-Based Biding in High-Level Synthesis (short paper)", in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016), R4-5, pp. 303-304 (Oct. 2016). [pdf]
• K. Nakamura and N. Ishiura: "Random Testing of C Compilers Based on Test Program Generation by Equivalence Transformation," in Proc. Asia and Pacific Conference on Circuits and Systems (APCCAS 2016), pp. 676-679 (Oct. 2016). [pdf]

Technical Reports

• (in Japanese) D. Fujiwara, N. Ishiura, R. Sakai, R. Aoki, and T. Ogawara: "Mainframe Assembly to C translation in Legacy Migration," Technical Report of IEICE, VLD2015-104, (Jan. 2016). [pdf]
• (in Japanese) N. Ito, N. Ishiura, H. Tomiyama, and H. Kanbara: "Binary Synthesis Implementing External Interrupt Handler as Independent Module," Technical Report of IEICE, VLD2015-106, (Jan. 2016). [pdf]
• (in Japanese) K. Nakamura and N. Ishiura: "Random Testing of C Compilers Using Test Program Generation Based on Equivalence Conversion," Technical Report of IEICE, VLD2015-112, (Feb. 2016). [pdf]
• (in Japanese) H. Takebayashi, N. Ishiura, K. Azuma, N. Yoshida, and H. Kanbara: "High-level Synthesis of Embedded Systems Controller from Erlang," Technical Report of IEICE, VLD2015-114, (Feb. 2016). [pdf]
• (in Japanese) M. Shimizu and N. Ishiura: "Speculative Execution in Distributed Controllers for High-Level Synthesis," IPSJ Design Automation Symposium 2016, pp. 56-61 (Sept. 2016). [pdf]

2015

Conference Papers (Refereed)

• N. Ito, N. Ishiura, H. Tomiyama, and H. Kanbara: "High-Level Synthesis from Programs with External Interrupt Handling," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), R1-3, pp. 10-15 (Mar. 2015). [pdf]
• K. Nakamura and N. Ishiura: "Introducing Loop Statements in Random Testing of C Compilers Based on Expected Value Calculation (short paper)", in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), R3-3, pp. 226-227 (Mar. 2015). [pdf]
• T. Saeki, J. Goto, and N. Ishiura: "Exploring Parameter-Type Compiler Options for Accelerating Program Execution," in Proc. International Technical Conference on Circuit/Systems, Computers and Communications (ITC-CSCC 2015), pp. 725-727 (July 2015). [pdf]

Technical Reports

• (in Japanese) Y. Hibino and N. Ishiura: "CF3: Test suite for arithmetic optimization of C compilers," Technical Report of IEICE, VLD2013-133, (Jan. 2015). [pdf]
• (in Japanese) A. Hashimoto and N. Ishiura: "Detecting Missed Arithmetic Optimization Opportunities Using Random Testing of C Compilers," Technical Report of IEICE, VLD2014-130, (Jan. 2015). [pdf]
• (in Japanese) M. Shimizu and N. Ishiura: "Extending Distributed Control for High-Level Synthesis beyond Boundaries of Dataflow Graphs," Technical Report of IEICE, VLD2015-61, (Dec. 2015). [pdf]
• (in Japanese) J. Goto and N. Ishiura: "Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement," Technical Report of IEICE, VLD2015-74, (Dec. 2015). [pdf]

2014

Journal Papers

• E. Nagai, A. Hashimoto, and N. Ishiura: "Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions," IPSJ Transactions on System LSI Design Methodology, vol. 7, pp. 91-100 (Aug. 2014). [link]

Conference Papers (Refereed)

• N. Ishiura, H. Kanbara, and H. Tomiyama: "ACAP: Binary Synthesizer Based on MIPS Object Codes," in Proc. International Technical Conference on Circuit/Systems, Computers and Communications (ITC-CSCC 2014), pp. 725-728 (July 2014). [pdf]

Technical Reports

• (in Japanese) S. Yamashita and N. Ishiura: "Dynamic Operation Binding in Distributed Controller for Supporting Functional Units with Variable Latency," Technical Report of IEICE, VLD2013-128, (Jan. 2014). [pdf]
• (in Japanese) T. Fukumoto and N. Ishiura: "PerCUDA: CUDA Binding Framework for Perl," Technical Report of IEICE, VLD2013-132, (Jan. 2014). [pdf]
• (in Japanese) S. Tamura, N. Ishiura, H. Kanbara, and H. Tomiyama: "Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU," Technical Report of IEICE, VLD2013-133, (Jan. 2014). [pdf]
• (in Japanese) N. Ito, N. Ishiura, H. Tomiyama, and H. Kanbara: "Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU," IPSJ Design Automation Symposium 2014, pp. 121-126 (Aug. 2014). [pdf]

2013

Conference Papers (Refereed)

• E. Nagai, A. Hashimoto, and N. Ishiura: "Scaling up Size and Number of Expressions in Random Testing of Arithmetic Optimization of C Compilers," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2013), R2-3, pp. 88-93 (Oct. 2013). [pdf]

Technical Reports

• (in Japanese) E. Nagai, A. Hashimoto, and N. Ishiura: "Scaling the size of Expressions in Random Testing of Arithmetic Optimization of C Compilers," Technical Report of IEICE, VLD2012-117, (Jan. 2013). [pdf]
• (in Japanese) S. Satake, N. Ishiura, S. Tamura, H. Kanbara, and H. Tomiyama: "Speeding up Multiple Sections of Binary Code by Hardware Accelerator Tightly Coupled with CPU," Technical Report of IEICE, VLD2012-119, (Jan. 2013). [pdf]

2012

Conference Papers (Refereed)

• T. Kumura, S. Taga, N. Ishiura, Y. Takeuchi, and M. Imai: "Automatic Generation of GNU Binutils and GDB for Custom Processors Based on Plug-in Method," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2012), R1-8, pp. 36-41 (Mar. 2012). [pdf]
• T. Fukumoto, K. Morimoto, and N. Ishiura: "Accelerating Regression Test of Compilers by Test Program Merging," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2012), R1-9, pp. 42-47 (Mar. 2012). [pdf]
• E. Nagai, H. Awazu, N. Ishiura, and N. Takeda: "Random Testing of C Compilers Targeting Arithmetic Optimization," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2012), R1-10, pp. 48-53 (Mar. 2012). [pdf]
• T. Kumura, Y. Nakamura, N. Ishiura, Y. Takeuchi, and M. Imai: "Model Based Parallelization from the Simulink Models and Their Sequential C Code," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2012), R2-8, pp. 186-191 (Mar. 2012). [pdf]

Technical Reports

• (in Japanese) F. Takashima, N. Ishiura, M. Orino, H. Tomiyama, and H. Kanbara: "Merge of Functions in High-Level Synthesis Using Assembly Codes as Intermediate Representation," Technical Report of IEICE, VLD2011-106, (Jan. 2012). [pdf]
• (in Japanese) M. Orino, N. Ishura, H. Tomiyama, F. Takashima, and H. Kanbara: "High-Level Synthesis of Hardware Relinkable to Softoware," Technical Report of IEICE, VLD2011-107, (Jan. 2012). [pdf]

2011

Technical Reports

• (in Japanese) K. Sone and N. Ishiura: "Approximated Variable Scheduling for High-Level Synthesis," Technical Report of IEICE, VLD2010-90, (Jan. 2011). [pdf]
• (in Japanese) K. Morimoto, N. Ishiura, Y. Uchiyama, and N. Hikichi: "Acceleration of Regression Test of Compilers by Program Merging," Technical Report of IEICE, VLD2010-94, (Jan. 2011). [pdf]
• (in Japanese) S. Taga, T. Kumura, N. Ishiura, Y. Takeuchi, and M. Imai: "Automatic Retargeting of Binutils and GDB Based on Plug-in Method," Technical Report of IEICE, VLD2010-95, (Jan. 2011). [pdf]
• (in Japanese) N. Ishiura, M. Makino, K. Usami, I. Yamada, K. Hiraishi, S. Yamaguchi, and M. Nakamura: "[Panel Discussion] Toward new developments of System and Signal Processing Subsociety," Technical Report of IEICE, CAS2011-22 VLD2011-29, SIP2011-51, MSS2011-22, (June 2011). [pdf]

2010

Journal Papers

• M. Imai, Y. Takeuchi, K. Sakanushi, and N. Ishiura: "Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)", IPSJ Transactions on System LSI Design Methodology, vol. 3, pp. 161-178 (Aug. 2010). [pdf]
• T. Kumura, S. Taga, N. Ishiura, Y. Takeuchi, and M. Imai: "Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors," IPSJ Transactions on System LSI Design Methodology, vol. 3, pp. 207-221 (Aug. 2010). [pdf]

Technical Reports

• (in Japanese) Y. Toda, N. Ishiura, H. Kanbara, and H. Tomiyama: "Hardware/Software Co-Design Based on Coprocessor Tightly Coupled with CPU," IPSJ SIG Technical Report, 2010-ARC-187-16/2010-EMB-15-16, (Jan. 2010). [pdf]
• (in Japanese) T. Kumura, S. Taga, N. Ishiura, Y. Takeuchi, and M. IMAI: "Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors," Technical Report of IEICE, VLD2009-120, (Mar. 2010). [pdf]
• (in Japanese) Y. Iritani, T. Ikegami, N. Ishiura, H. Kanbara, and H. Tomiyama: "Implementation of a High-Level Synthesis System which Uses MIPS Assembly Programs as Intermediate Representation," IPSJ SIG Technical Report, 2010-SLDM-144-58/2010-EMB-16-58, (Mar. 2010). [pdf]

2009

Conference Papers (Refereed)

• Y. Toda, N. Ishiura, and K. Sone: "Static Scheduling of Dynamic Execution for High-Level Synthesis," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2009), pp. 107-112 (Mar. 2009). [pdf] Outstanding Paper Award

Technical Reports

• (in Japanese) Y. Ishimori, N. Ishiura, H. TOmiyama, and H. Kanbara: "Extension of High Level Synthesis System CCAP for AMP Multi-Core System Design," Technical Report of IEICE, VLD2008-105/CPSY2008-67/RECONF2008-69, pp. 81-86 (Jan. 2009). [pdf]
• (in Japanese) T. Yamamoto, N. Ishiura, T. Kumura, M. Ikekawa, and and: "Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution," Technical Report of IEICE, VLD2008-126, pp. 1-6 (Mar. 2009). [pdf]
• (in Japanese) H. Awazu and N. Ishiura: "Random Testing for Arithmetic Optimization of C Compilers," Technical Report of IEICE, VLD2008-127, pp. 7-10 (Mar. 2009). [pdf]

2008

Journal Papers

• M. Nishimura, N. Ishiura, Y. Ishimori, H. Kanbara, and H. Tomiyama: "High-level synthesis of software function Calls (Letter)", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3556-3558 (Dec. 2008). [pdf]

Technical Reports

• (in Japanese) S. Yoshida, T. Kumura, N. Ishiura, M. Ikekawa, and M. Imai: "Automatic Generation for GCC for Insturction Set Extension on Configurable Processor," IPSJ SIG Technical Report. 2008-ARC-176/2008-EMB-7, pp. 29-34 (Jan. 2008). [pdf]
• (in Japanese) T. Morimoto, T. Kumura, N. Ishiura, M. Ikekawa, and M. Imai: "VLIW Extention of Software Development Environment Construction Tool ArchC," Technical Report of IEICE, VLD2007-134/CPSY2007-77/RECONF2007-80, pp. 95-100 (Jan. 2008). [pdf]
• (in Japanese) Y. Toda, N. Ishiura, and K. SONE: "Variable Scheduling and Binding for High-Level Synthesis Considering Indefinite Cycle Operations," Technical Report of IEICE, VLD2008-83/DC2008-51, pp. 139-144 (Nov. 2008). [pdf]

2007

Conference Papers (Refereed)

• H. Kanbara, T. Nakatani, N. Umehara, N. Ishiura, and H. Tomiyama: "Speed Improvement of AES Encryption Using Hardware Accelerators Synthesized by C Compatible Architecture Prototyper (CCAP)", in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2007), pp. 130-134 (Oct. 2007). [pdf]
• M. Nishimura, N. Ishiura, Y. Ishimori, H. Kanbara, and H. Tomiyama: "Calling Software Functions from Hardware Functions in High-Level Synthesizer CCAP," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2007), pp. 357-360 (Oct. 2007). [pdf]

Technical Reports

• (in Japanese) R. Kobayashi, Y. Masui, and N. Ishiura: "Optimum code scheduling for clustered VLIW DSP using pseudo," Technical Report of IEICE. VLD2006-94/CPSY2006-65/RECONF2006-65, pp. 1-5 (Jan. 2007). [pdf]
• (in Japanese) Y. Uchiyama, N. Hikichi, N. Ishiura, and Y. Nagamatsu: "Test suite of C compilers and its generating tool "testgen"," Technical Report of IEICE. VLD2006-95/CPSY2006-66/RECONF2006-66, pp. 7-11 (Jan. 2007). [pdf]
• (in Japanese) H. Kanbara, N. Umehara, T. Nakatani, N. Ishiura, and H. Tomiyama: "Speed improvement of AES encryption using hardware accelerators synthesized by C compatible architecture prototyper(CCAP)", IPSJ SIG Technical Reports, 2007-ARC-171/2007-EMB-3, pp. 7-12 (Jan. 2007). [pdf]
• (in Japanese) M. Nishimura, N. Ishiura, Y. Ishimori, H. Kanbara, and H. Tomiyama: "Calling software functions from hardware functions in high level synthesizer CCAP," IPSJ SIG Technical Reports, 2007-ARC-171/2007-EMB-3, pp. 13-18 (Jan. 2007). [pdf]
• (in Japanese) (M. M. Fukui, (P. N. Ishiura, T. Izumi, and A. Yamada: "[Panel Discussion] High-Level Synthesis; Will it be Useful or Useless?", IPSJ SIG Technical Report. 2007-SLDM-130, p. 31 (May 2007). [pdf]
• (in Japanese) Y. Masui and N. Ishiura: "Cycle Partitioned Scheduling for Code Optimization of VLIW DSP," IEICE Technical Reports, VLD2007-102/DC2007-57, pp. 79-84 (Nov. 2007). [pdf]
• (in Japanese) S. Nogaito, N. Ishiura, and M. Imai: "Retargetable Linear Assembler for VLIW Processor," IEICE Technical Reports, VLD2007-103/DC2007-58, pp. 85-90 (Nov. 2007). [pdf]

2006

Conference Papers (Refereed)

• M. Nishimura, K. Nishiguchi, N. Ishiura, H. Kanbara, H. Tomiyama, Y. Takatsukasa, and M. Kotani: "High-level synthesis of variable accesses and function calls in software compatible hardware synthesizer CCAP," in Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2006), pp. 29-34 (Apr. 2006). [pdf]

Technical Reports

• (in Japanese) Y. Nagamatsu, N. Ishiura, and N. Hikichi: "Retargeting GCC and GNU toolchain for extended instruction set," Technical Report of IEICE. VLD2005-103/CPSY2005-59/RECONF2005-92, pp. 37-41 (Jan. 2006). [pdf]

2005

Technical Reports

• (in Japanese) Y. Hiraoka, N. Ishiura, and M. Imai: "Extraction of instruction latency from cycle-true processor models," Technical Report of IEICE. VLD2004-119/CPSY2004-85, pp. 55-60 (Jan. 2005). [pdf]
• (in Japanese) A. Kishimoto, N. Ishiura, and M. Imai: "Instruction pattern generation for retargetable compiler," Technical Report of IEICE. VLD2004-120/CPSY2004-86, pp. 61-66 (Jan. 2005). [pdf]
• (in Japanese) K. Nishiguchi, N. Ishiura, M. Nishimura, H. Kanbara, H. Tomiyama, Y. Takatsukasa, and M. Kotani: "Handling of variables and functions for software compatible hardware synthesizer CCAP," Technical Report of IEICE. VLD2005-79/ICD2005-174/DC2005-56, pp. 19-24 (Dec. 2005). [pdf]

2004

2002

Conference Papers (Refereed)

• N. Ishiura and T. Watanabe: "Datapath oriented codesign method of application specific DSPs using retargetable compiler," in Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2002), vol. 1, pp. 55-58 (Dec. 2002).

2001

Journal Papers

• T. Watanabe and N. Ishiura: "Register constraint analysis to minimize spill code for application specific DSPs (Letter)", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E84-A, no. 6, pp. 1541-1544 (June 2001). [pdf]

2000

Journal Papers

• M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe: "Thread composition method for hardware compiler Bach maximizing resource sharing among processes," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E83-A, no. 12, pp. 2456-2463 (Dec. 2000).

Conference Papers (Refereed)

• M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe: "Thread partitioning method for hardware compiler Bach," in Proc. Asia and South Pacific Design Automation Conference 2000 (ASP-DAC 2000), pp. 303-308 (Jan. 2000).
• N. Ishiura, T. Watanabe, and M. Yamaguchi: "A code generation method for datapath oriented application specific processor design," in Proc. Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI 2000), pp. 71-78 (Apr. 2000).

Technical Reports

• (in Japanese) T. Watanabe, N. Ishiura, and M. Yamaguchi: "A code generation method for datapath oriented codesign of application specific DSPs," Proc. IEICE 13th Karuizawa Workshop on Circuits and Systems, pp. 539-544 (Apr. 2000).
• (in Japanese) T. Watanabe and N. Ishiura: "Datapath oriented codesign method of application specific DSPs by retargetable compiler," Technical Report of IEICE. VLD2000-89, ICD2000-146, FTS2000-54, pp. 119-124 (Nov. 2000).

1999

Conference Papers (Refereed)

• N. Ishiura and M. Yamaguchi: "Operation binding for retargetable compilers minimizing clock cycles," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), pp. 705-708 (July 1999).

Technical Reports

• (in Japanese) M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe: "Thread partitioning method for hardware compiler bach," Proc. IEICE 12th Karuizawa Workshop on Circuits and Systems, pp. 103-108 (Apr. 1999).
• (in Japanese) T. Watanabe, N. Ishiura, and M. Yamaguchi: "Scheduling algorithm of retargetable compiler for non-orthogonal datapaths," Proc. IEICE 12th Karuizawa Workshop on Circuits and Systems, pp. 109-114 (Apr. 1999).

1998

Journal Papers

• M. Yamaguchi, N. Ishiura, and T. Kambe: "A binding algorithm for retargetable compilation to non-orthogonal DSP architectures," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E81-A, no. 12, pp. 2630-2639 (Dec. 1998).

Conference Papers (Refereed)

• M. Yamaguchi, N. Ishiura, and T. Kambe: "Binding and scheduling algorithms for highly retargetable compilation," in Proc. Asia and South Pacific Design Automation Conference 1998 (ASP-DAC '98), pp. 93-98 (Feb. 1998).
• M. Yamaguchi, N. Ishiura, and T. Kambe: "A binding algorithm for retargetable compilation to non-orthogonal datapath architectures," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '98), (June 1998).
• N. Ishiura, M. Yamaguchi, and N. Nitta: "Field partitioning algorithms for compression of instruction codes of application specific VLIW processors," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98), pp. 1387-1390 (July 1998).
• N. Ishiura, M. Yamaguchi, and T. Kambe: "A graph-based algorithm of operation binding for compilers targeting heterogeneous datapath," in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 395-398 (Nov. 1998).

Technical Reports

• (in Japanese) M. Yamaguchi, N. Ishiura, and T. Kambe: "A binding algorithm for retargetable compiler to non-orthogonal datapaths," Proc. IEICE 11th Karuizawa Workshop on Circuits and Systems, pp. 481-486 (Apr. 1998).
• (in Japanese) Y. Hattori, N. Ishiura, and M. Yamaguchi: "Operation and transfer binding of retargetable compilation for DSP," Technical Report of IEICE. VLD98-125/CPSY98-145, pp. 55-62 (Dec. 1998).

1997

Journal Papers

• S. Yano, K. Akagi, H. Inohara, and N. Ishiura: "Application of full scan design to embedded memory arrays," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E80-A, no. 3, pp. 514-520 (Mar. 1997).
• M. Yamaguchi, A. Yamada, T. Nakaoka, T. Kambe, and N. Ishiura: "Architecture evaluation based on the datapath structure and parallel constraint," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E80-A, no. 10, pp. 1853-1860 (Oct. 1997).
• S. Yano and N. Ishiura: "Embedded memory array testing using a scannable configuration," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E80-A, no. 10, pp. 1934-1944 (Oct. 1997).

Conference Papers (Refereed)

• S. Yano and N. Ishiura: "Memory array testing through a scannable configuration," in Proc. IEEE International Workshop on Memory Technology, Design and Testing, pp. 87-94 (Aug. 1997).
• N. Ishiura and M. Yamaguchi: "Instruction code compression for application specific VLIW processors based on automatic field partitioning," in Proc. International Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI '97), pp. 105-109 (Aug. 1997). [pdf]

Technical Reports

• (in Japanese) S. Yano and N. Ishiura: "Testing embedded memory array through a scannable configuration," Proc. IEICE 10th Karuizawa Workshop on Circuits and Systems, pp. 95-100 (Apr. 1997).
• (in Japanese) M. Yamaguchi, N. Ishiura, and T. Kambe: "A Method of Retargetable Compilation for Embedded Systems," Technical Report of IEICE. VLD97-90/FTS97-53, pp. 85-92 (Oct. 1997).
• (in Japanese) T. Yamamoto, N. Ishiura, M. Yamaguchi, and Y. Hattori: "A high-level synthesis system for embeded system," Technical Report of IEICE. VLD97-91/FTS97-54, pp. 93-100 (Oct. 1997).

1996

Journal Papers

• H. Yamauchi, N. Ishiura, and H. Takahashi: "Implicit representation and manipulation of binary decision diagrams," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E79-A, no. 3, pp. 354-362 (Mar. 1996). [pdf]
• (in Japanese) S. Yano and N. Ishiura: "Application of scan path approach to sequential circuits including memory arrays (in English)", IEICE Trans. Information and Systems, vol. J79-D-I, no. 12, pp. 1055-1062 (Dec. 1996).

Conference Papers (Refereed)

• S. Nakamura, N. Ishiura, T. Yamamoto, and I. Shirakawa: "High-level synthesis system for behavioral description with conditional branches," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '96), pp. 935-938 (July 1996).
• Y. Konno, K. Nakamura, T. Bitoh, K. Saga, and S. Yano: "A consistent scan design system for large-scale ASICs," in Proc. Fifth Asian Test Symposium (ATS '96), pp. 82-87 (Nov. 1996).

Technical Reports

• S. Yano, K. Akagi, and N. Ishiura: "A new scan path approach to memory array testing," Proc. IEICE 9th Karuizawa Workshop on Circuits and Systems, pp. 55-60 (Apr. 1996).

1995

Conference Papers (Refereed)

• A. Yamada, S. Nakamura, N. Ishiura, I. Shirakawa, and T. Kambe: "Optimal scheduling for conditional resource sharing," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '95), pp. 2297-2300 (Apr. 1995).

Technical Reports

• (in Japanese) H. Yamauchi, N. Ishiura, and H. Takahashi: "Implicit representation and manipulation of binary decision diagrams," Technical Report of IEICE. CAS94-126/VLD94-142/ICD94-250, pp. 41-48 (Mar. 1995). [pdf]
• (in Japanese) H. Yamaguchi, N. Ishiura, and H. Takahashi: "Implicit representation and manipulation of binary decision diagrams," Proc. IEICE 8th Karuizawa Workshop on Circuits and Systems, pp. 287-292 (Apr. 1995). [pdf]

1994

Journal Papers

• N. Takahashi, N. Ishiura, and S. Yajima: "Fault simulation for multiple faults by Boolean function manipulation," IEEE Trans. Computer-Aided Design, vol. 13, no. 4, pp. 531-535 (Apr. 1994).
• A. Yamada, T. Yamazaki, N. Ishiura, I. Shirakawa, and T. Kambe: "Datapath scheduling for behavioral description with conditional branches," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E77-A, no. 12, pp. 1999-2009 (Dec. 1994).

Conference Papers (Refereed)

• A. Yamada, T. Yamazaki, N. Ishiura, I. Shirakawa, and T. Kambe: "Datapath Scheduling Based on Integer Nonlinear Programming," in Proc. IEICE 1994 Symposium on Nonlinear Theory and its Applications, pp. 291-294 (Oct. 1994).
• A. Yamada, T. Yamazaki, N. Ishiura, T. Kambe, and I. Shirakawa: "Datapath scheduling for conditional resource sharing," in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '94), pp. 169-174 (Dec. 1994).

1993

Journal Papers

• (in Japanese) H. Sawada, N. Ishiura, and S. Yajima: "Minimization of binary decision diagrams representing Boolean functions (in Japanese)", IEICE Trans. Information and Systems, vol. J76-D-I, no. 2, pp. 63-71 (Feb. 1993).
• (in Japanese) Y. Deguchi, N. Ishiura, and S. Yajima: "Analysis of timing error probability using probabilistic coded time-symbolic simulation (in Japanese)", Trans. IPS Japan, vol. 34, no. 5, pp. 1125-1133 (May 1993).
• (in Japanese) H.-Y. Choi, T. Kohara, N. Ishiura, I. Shirakawa, and A. Motohara: "Test generation for sequential circuits based on Boolean function manipulation (in Japanese)", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. J76-A, no. 6, pp. 835-843 (June 1993).
• H.-Y. Choi, T. Kohara, N. Ishiura, and I. Shirakawa: "Test generation for sequential circuits using shared binary decision diagram," Kite Journal of Electronics Engineering, vol. 4, no. 1A, pp. 80-88 (July 1993).
• I. Shirakawa and N. Ishiura: "Research topics and results on simulation for VLSI (invited paper)", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E76-A, no. 7, pp. 1070-1076 (July 1993).
• N. Ishiura: "Synthesis of multilevel logic circuits from binary decision diagrams," IEICE Trans. Information and Systems, vol. E76-D, no. 9, pp. 1085-1092 (Sept. 1993). [pdf]
• H. Higuchi, N. Ishiura, and S. Yajima: "Compaction of test sets for combinational circuits based on symbolic fault simulation," IEICE Trans. Information and Systems, vol. E76-D, no. 9, pp. 1121-1127 (Sept. 1993).
• H.-Y. Choi, H. Maeda, T. Kohara, N. Ishiura, I. Shirakawa, and A. Motohara: "Test generation for sequential circuits using partitioned image computation," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E76-A, no. 10, pp. 1770-1774 (Oct. 1993).

Tutorials

• (in Japanese) N. Ishiura: "An introduction to binary decision diagrams," IPSJ Magazine, vol. 34, no. 5, pp. 585-592 (May 1993).

Technical Reports

• (in Japanese) N. Ishiura, M. Takatsu, and I. Shirakawa: "Synthesis of multi-level logic circuits from binary decision diagrams based on prefix computation tree," Proc. IEICE 6th Karuizawa Workshop on Circuits and Systems, pp. 207-212 (Apr. 1993).
• (in Japanese) H.-Y. Choi, H. Maeda, T. Kohara, N. Ishiura, I. Shirakawa, and A. Motohara: "Test generation for sequential circuits using approximate Boolean function manipulation," Proc. IEICE 6th Karuizawa Workshop on Circuits and Systems, pp. 213-218 (Apr. 1993).

1992

Journal Papers

• N. Ishiura and S. Yajima: "Linear time fault simulation algorithm using a content addressable memory (invited paper)", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E75-A, no. 3, pp. 314-320 (Mar. 1992).
• N. Ishiura, Y. Deguchi, and S. Yajima: "Coded time-symbolic simulation for timing verification of logic circuits," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E75-A, no. 10, pp. 1247-1254 (Oct. 1992).

Conference Papers (Refereed)

• N. Ishiura: "Synthesis of multi-level logic circuits from binary decision diagrams," in Proc. Synthesis and Simulation Meeting and International Interchange (SASIMI '92), pp. 74-83 (Apr. 1992).
• H. Higuchi, N. Ishiura, and S. Yajima: "Compaction of test sets based on symbolic fault simulation," in Proc. Synthesis and Simulation Meeting and International Interchange (SASIMI '92), pp. 253-262 (Apr. 1992).
• H.-Y. Choi, T. Kohara, N. Ishiura, and I. Shirakawa: "Test generation for sequential circuits based on Boolean function manipulation," in Proc. Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '92), pp. 248-253 (July 1992).
• N. Ishiura and S. Yajima: "Linear time fault simulation algorithm using a content addressable memory," in Proc. European Design Automation Conference (EURO-DAC '92), pp. 442-445 (Sept. 1992).

Technical Reports

• (in Japanese) N. Ishiura: "A report of ICCAD," Report of Technical Group on Design Automation, IPS Japan,　61-6, pp. 1-4 (Feb. 1992).
• (in Japanese) N. Ishiura: "An introduction to binary decision diagrams," Proc. IEICE 5th Karuizawa Workshop on Circuits and Systems, pp. 155-160 (Apr. 1992).
• (in Japanese) H. Choi, T. Kohara, N. Ishiura, and I. Shirakawa: "Test Generation for Sequential Circuits Using Shared Binary Decision Diagrams," Technical Report of IEICE. CAS92-28/VLD92-28/DSP92-39, pp. 61-66 (May 1992).
• (in Japanese) Y. Shimosakoda, N. Ishiura, and I. Shirakawa: "A fast fault simulation method using multi decision diagram representation," Technical Report of IEICE. CAS92-29/VLD92-29/DSP92-40, pp. 67-72 (May 1992).

1991

Journal Papers

• (in Japanese) S.-ichi Minato, N. Ishiura, and S. Yajima: "Shared binary decision diagrams for efficient Boolean function manipulation (in Japanese)", Trans. IPS Japan, vol. 32, no. 1, pp. 77-85 (Jan. 1991).
• (in Japanese) O. Karatsu, T. Hoshino, N. Ishiura, and H. Yasuura: "UDL/I: A hardware design language standard for logic synthesis age (in Japanese, invited paper)", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. J74-A, no. 2, pp. 170-178 (Feb. 1991).
• H. Ochi, N. Ishiura, and S. Yajima: "A vector algorithm for manipulating Boolean functions based on shared binary decision diagrams," SUPERCOMPUTER, vol. 46, no. VIII-6, pp. 101-118 (Nov. 1991).

Conference Papers (Refereed)

• H. Ochi, N. Ishiura, and S. Yajima: "Breadth-first manipulation of SBDD of Boolean functions for vector processing," in Proc. ACM/IEEE Design Automation Conference, pp. 413-416 (June 1991).
• Y. Deguchi, N. Ishiura, and S. Yajima: "Probabilistic CTSS: Analysis of timing error probability in asynchronous logic circuits," in Proc. ACM/IEEE Design Automation Conference, pp. 650-655 (June 1991).
• H. Ochi, N. Ishiura, and S. Yajima: "A vector algorithm for manipulating Boolean functions based on shared binary decision diagrams," in Proc. International Symposium on Supercomputing, pp. 191-200 (Nov. 1991).
• N. Ishiura, H. Sawada, and S. Yajima: "Minimization of binary decision diagrams based on exchanges of variables," in Proc. IEEE International Conference on Computer-Aided Design (ICCAD-91), pp. 472-475 (Nov. 1991).
• M. Takahashi, N. Ishiura, and S. Yajima: "Fault simulation for multiple faults using shared BDD representation of fault sets," in Proc. IEEE International Conference on Computer-Aided Design (ICCAD-91), pp. 550-553 (Nov. 1991).

Technical Reports

• H. Ochi, N. Ishiura, N. Takagi, and S. Yajima: "A breadth-first vector algorithm for manipulating SBDD," ?, pp. 1-8 (Jan. 1991).
• (in Japanese) N. Ishiura and S. Yajima: "A class of logic functions expressible by polynomial-size binary decision diagrams," LA Symposium, pp. 1-7 (Jan. 1991).
• (in Japanese) N. Ishiura and S. Yajima: "A class of logic functions expressible by polynomial-size binary decision diagrams (in Japanese)", ?, pp. 1-7 (Mar. 1991).
• (in Japanese) N. Ishiura and S. Yajima: "Linear time fault simulation using a content addressable memory," Proc. IEICE 4th Karuizawa Workshop on Circuits and Systems, pp. 63-68 (Apr. 1991).
• (in Japanese) H. Sawada, N. Ishiura, and S. Yajima: "Minimization of binary decision diagrams representing Boolean functions," Technical Report of IEICE. COMP91-15, pp. 27-36 (May 1991).
• (in Japanese) H. Higuchi, N. Ishiura, and S. Yajima: "Generation of compact test sets based on symbolic fault simulation," Technical Report of IEICE. FTS91-28, pp. 71-78 (July 1991).
• (in Japanese) N. Ishiura and S. Yajima: "Linear time fault simulation algorithm using a content addressable memory," Technical Report of IEICE. FTS91-29, pp. 79-86 (July 1991).
• (in Japanese) H. Sawada, N. Ishiura, and S. Yajima: "Variable ordering of binary decision diagrams," ?, pp. 1-8 (July 1991).
• (in Japanese) N. Ishiura: "Synthesis of combinational logic circuits from binary decision diagrams," Report of Technical Group on Design Automation, IPS Japan, 60-20, pp. 155-161 (Dec. 1991).

1990

Journal Papers

• N. Ishiura, M. Ito, and S. Yajima: "Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor," IEEE Trans. Computer-Aided Design, vol. 9, no. 8, pp. 868-875 (Aug. 1990).
• (in Japanese) N. Ishiura, M. Takahashi, and S. Yajima: "Time-symbolic simulation for accurate timing verification of logic circuits (in Japanese)", Trans. IPS Japan, vol. 31, no. 12, pp. 1832-1839 (Dec. 1990).

Conference Papers (Refereed)

• N. Ishiura, H. Yasuura, and S. Yajima: "NES: The behavioral model for the formal semantics of a hardware design language UDL/I," in Proc. ACM/IEEE Design Automation Conference, pp. 8-13 (June 1990).
• S.-ichi Minato, N. Ishiura, and S. Yajima: "Shared binary decision diagram with attributed edges for efficient Boolean function manipulation," in Proc. ACM/IEEE Design Automation Conference, pp. 52-57 (June 1990).
• N. Ishiura, Y. Deguchi, and S. Yajima: "Coded time-symbolic simulation using shared binary decision diagram," in Proc. ACM/IEEE Design Automation Conference, pp. 130-135 (June 1990).
• H. Yasuura and N. Ishiura: "Formal semantics of UDL/I and its applications to CAD/DA tools," in Proc. IEEE International Conference on Computer Design (ICCD '90), pp. 90-94 (Sept. 1990).
• N. Ishiura and S. Yajima: "A class of logic functions expressible by polynomial-size binary decision diagrams," in Proc. Synthesis and Simulation Meeting and International Interchange (SASIMI '90), pp. 48-54 (Oct. 1990). [pdf]
• Y. Deguchi, N. Ishiura, and S. Yajima: "Coded time-symbolic simulation: Simulation of logic circuits with nondeterministic delays based on Boolean function manipulation," in Proc. Synthesis and Simulation Meeting and International Interchange (SASIMI '90), pp. 149-156 (Oct. 1990).
• N. Takahashi, N. Ishiura, and S. Yajima: "Fault simulation for multiple faults using shared binary decision diagrams," in Proc. Synthesis and Simulation Meeting and International Interchange (SASIMI '90), pp. 157-164 (Oct. 1990).

Technical Reports

• (in Japanese) Y. Deguchi, N. Ishiura, and S. Yajima: "Analysis of timing error probability based on coded time-symbolic simulation (in Japanese)", Report of Technical Group on VLSI Design Technology, IEICE, VLD90-89, pp. 65-72 (Dec. 1990).
• (in Japanese) N. Takahashi, N. Ishiura, and ShuzoYajima: "Fault simulation for multiple faults using shared binary decision diagrams (in Japanese)", Report of Technical Group on VLSI Design Technology, IEICE, VLD90-93, pp. 23-30 (Dec. 1990).

1989

Conference Papers (Refereed)

• N. Ishiura, M. Takahashi, and S. Yajima: "Time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuits," in Proc. ACM/IEEE Design Automation Conference, pp. 497-502 (June 1989).
• H. Yasuura and N. Ishiura: "Semantics of a hardware design language for Japanese standardization," in Proc. ACM/IEEE Design Automation Conference, pp. 836-839 (June 1989).
• S.-ichi Minato, N. Ishiura, and S. Yajima: "Fast tautology checking using shared binary decision diagram --- Benchmark results ---," in Proc. IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, vol. 2, pp. 107-111 (Nov. 1989).

Technical Reports

• (in Japanese) N. Ishiura and S. Yajima: "A nondeterministic behavior model for definition of formal semantics of hardware description languages (in Japanese)", Report of Technical Group on VLSI Design Technology, IEICE, FTS89-3/VLD89-3, pp. 15-22 (Apr. 1989).
• (in Japanese) S.-ichi Minato, N. Ishiura, and S. Yajima: "," , (Aug. 1989).
• (in Japanese) Y. Komura, N. Ishiura, and S. Yajima: "Formal semantics of hardware description languages based on nondeterministic sequential machines (in Japanese)", Report of Technical Group on VLSI Design Technology, IEICE, VLD89-75, pp. 1-6 (Dec. 1989).
• (in Japanese) S.-ichi Minato, N. Ishiura, and S. Yajima: "Shared binary decision diagram for efficient Boolean function manipulation (in Japanese)", Report of Technical Group on VLSI Design Technology, IEICE, VLD89-80, pp. 39-46 (Dec. 1989).
• N. Ishiura, Y. Deguchi, and S. Yajima: "Coded time-symbolic simulation using shared binary decision diagram," Report of Technical Group on VLSI Design Technology, IEICE, VLD89-81, pp. 47-54 (Dec. 1989).

1988

Journal Papers

• (in Japanese) N. Ishiura, N. Takagi, and S. Yajima: "Sorting on a vector processor (in Japanese)", Trans. IPS Japan, vol. 29, no. 4, pp. 378-385 (Apr. 1988).
• (in Japanese) N. Ishiura, M. Ito, and S. Yajima: "Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor (in Japanese)", Trans. IPS Japan, vol. 29, no. 5, pp. 522-528 (May 1988).

Technical Reports

• (in Japanese) N. Ishiura and H. Yasuura: "On computational complexity of hazard detection oroblems of combinational logic circuits," , pp. 1-8 (Jan. 1988).
• (in Japanese) N. Ishiura and H. Yasuura: "On timing-models and accuracy in mix-level logic simulation," , pp. 193-200 (May 1988).
• (in Japanese) N. Ishiura and H. Yasuura: "On a relation between time-models and computationa time of hazard detection problems (in Japanese)", Report of Technical Group on Theoretical Foundations of Computing, IEICE, COMP88-21, pp. 45-52 (June 1988).
• (in Japanese) M. Ito, N. Ishiura, and S. Yajima: "Test generation using a fast fault simulator on a vector processor (in Japanese)", Report of Technical Group on VLSI Design Technology, IEICE, VLD88-27, pp. 23-28 (July 1988).
• (in Japanese) N. Ishiura and H. Yasuura: "On computational complexity of hazard detection problems of combinational circuits (in Japanese)", RIMS Koukyuroku, vol. 666, pp. 51-60 (July 1988).
• (in Japanese) M. Takahashi, N. Ishiura, and S. Yajima: "," , pp. 1-6 (Aug. 1988).
• (in Japanese) M. Takahashi, N. Ishiura, and S. Yajima: "Result-analysis system for time-symbolic logic simulation (in Japanese)", Report of Technical Group on Design Automation, IPS Japan, 44-2, pp. 9-16 (Oct. 1988).

1987

Journal Papers

• N. Ishiura, H. Yasuura, and S. Yajima: "High-speed logic simulation on vector processors," IEEE Trans. Computer-Aided Design, vol. CAD-6, no. 3, pp. 305-321 (May 1987).

Conference Papers (Refereed)

• N. Ishiura, M. Ito, and S. Yajima: "High-speed fault simulation using a vector processor," in Proc. IEEE International Conference on Computer-Aided Design (ICCAD-87), pp. 10-13 (Nov. 1987).

Technical Reports

• (in Japanese) H. Yasuura and N. Ishiura: "On computational complexity of hazard detection problems (in Japanese)", Report of Technical Group on Theoretical Foundations of Computing, IEICE, COMP86-64, pp. 29-37 (Jan. 1987).
• (in Japanese) N. Ishiura, N. Takagi, and S. Yajima: "Sorting on vector processors (in Japanese)", Report of Technical Group on Theoretical Foundations of Computing, IEICE, COMP86-88, pp. 79-86 (Mar. 1987).
• (in Japanese) N. Ishiura, M. Ito, H. Yasuura, and S. Yajima: "On dynamic 2-dimensional parallel fault simulation on a vector processor (in Japanese)", Report of Technical Group on VLSI Design Technology, IEICE, VLD87-2, pp. 9-16 (Apr. 1987).
• (in Japanese) N. Ishiura, Y. Komura, and S. Yajima: "," , pp. 1-5 (Aug. 1987).
• (in Japanese) N. Ishiura and S. Yajima: "On time-symbolic simulation (in Japanese)", Report of Technical Group on VLSI Design Technology, IEICE, VLD87-112, pp. 39-46 (Dec. 1987).

1986

Journal Papers

• (in Japanese) N. Ishiura, H. Yasuura, and S. Yajima: "High-speed logic simulation using a vector processor," Trans. IPS Japan, vol. 27, no. 5, pp. 510-517 (May 1986).

Technical Reports

• (in Japanese) N. Ishiura, M. Kume, H. Yasuura, and S. Yajima: "Parallel fault simulation using a vector processor (in Japanese)", Report of Technical Group on Fault Tolerant Systems, IECE, FTS86-4, pp. 25-30 (May 1986).
• (in Japanese) N. Ishiura, H. Yasuura, and S. Yajima: "Performance evaluation of logic simulator on vector processors (in Japanese)", Report of Technical Group on Circuit and Systems, IECE, CAS86-82, pp. 25-32 (Sept. 1986).

1985

Journal Papers

• (in Japanese) N. Ishiura, H. Yasuura, and S. Yajima: "High-speed logic simulation by time first evaluation algorithm," Trans. IPS Japan, vol. 26, no. 3, pp. 459-466 (May 1985).

Conference Papers (Refereed)

• N. Ishiura, H. Yasuura, T. Kawata, and S. Yajima: "High-speed logic simulation using a vector processor," in Proc. IFIP International Conference on Very Large Scale Integration (VLSI85), pp. 73-82 (Aug. 1985).
• N. Ishiura, H. Yasuura, T. Kawata, and S. Yajima: "High-speed logic simulation on a vector processor," in Proc. IEEE International Conference on Computer-Aided Design (ICCAD-85), pp. 119-121 (Nov. 1985).

Technical Reports

• (in Japanese) N. Ishiura, H. Yasuura, T. Kawata, and S. Yajima: "High-speed logic simulation using a vector processor (in Japanese)", Report of Technical Group on Design Automation, IPS Japan 25-2, pp. 1-10 (Feb. 1985).

1984

Journal Papers

• (in Japanese) H. Yasuura, H. Kano, Y. Ooi, S. Kimura, N. Ishiura, and S. Yajima: "ISS: An interactive simulation with input constraints monitoring facility," Trans. IPS Japan, vol. 25, no. 2, pp. 285-292 (Mar. 1984).

Conference Papers (Refereed)

• N. Ishiura, H. Yasuura, and S. Yajima: "Time first evaluation algorithm for high-speed logic simulation," in Proc. IEEE International Conference on Computer-Aided Design (ICCAD-84), pp. 197-199 (Nov. 1984).

Technical Reports

• (in Japanese) N. Ishiura, H. Yasuura, and S. Yajima: "High-speed logic simulation by time first evaluation algorithm (in Japanese)", Report of Technical Group on Electric Computers, IECE, EC84-49, pp. 49-59 (Dec. 1984).

1982

Technical Reports

• (in Japanese) H. Kano, Y. Ooi, S. Kimura, N. Ishiura, H. Yasuura, and S. Yajima: "ISS: Interactive logic design and verification support system (in Japanese)", Report of Technical Group on Design Automation, IPS Japan 15-1, pp. 1-8 (Dec. 1982).